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<title>CMSIS-Core (Cortex-M): Interrupts and Exceptions (NVIC)</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.6.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="header">
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<a href="#define-members">Macros</a> &#124;
<a href="#enum-members">Enumerations</a> &#124;
<a href="#func-members">Functions</a>  </div>
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<div class="title">Interrupts and Exceptions (NVIC)</div>  </div>
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<p>Functions to access the Nested Vector Interrupt Controller (NVIC).  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gadc48b4ed09386aab48fa6b9c96d9034c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a></td></tr>
<tr class="memdesc:gadc48b4ed09386aab48fa6b9c96d9034c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Virtualization of the NVIC API.  <a href="#gadc48b4ed09386aab48fa6b9c96d9034c">More...</a><br/></td></tr>
<tr class="separator:gadc48b4ed09386aab48fa6b9c96d9034c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad01d3aa220b50ef141b06c93888b268d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a></td></tr>
<tr class="memdesc:gad01d3aa220b50ef141b06c93888b268d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Virtualization of interrupt vector table access functions.  <a href="#gad01d3aa220b50ef141b06c93888b268d">More...</a><br/></td></tr>
<tr class="separator:gad01d3aa220b50ef141b06c93888b268d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> { <br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a> = -13, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a> = -12, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">BusFault_IRQn</a> = -11, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a> = -10, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da">SecureFault_IRQn</a> = -9, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a> = -4, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">WWDG_STM_IRQn</a> = 0, 
<br/>
&#160;&#160;<a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">PVD_STM_IRQn</a> = 1
<br/>
 }</td></tr>
<tr class="memdesc:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Definition of IRQn numbers.  <a href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">More...</a><br/></td></tr>
<tr class="separator:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gad78f447e891789b4d8f2e5b21eeda354"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a> (uint32_t PriorityGroup)</td></tr>
<tr class="memdesc:gad78f447e891789b4d8f2e5b21eeda354"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#gad78f447e891789b4d8f2e5b21eeda354">More...</a><br/></td></tr>
<tr class="separator:gad78f447e891789b4d8f2e5b21eeda354"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa81b19849367d3cdb95ac108c500fa78"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a> (void)</td></tr>
<tr class="memdesc:gaa81b19849367d3cdb95ac108c500fa78"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#gaa81b19849367d3cdb95ac108c500fa78">More...</a><br/></td></tr>
<tr class="separator:gaa81b19849367d3cdb95ac108c500fa78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga530ad9fda2ed1c8b70e439ecfe80591f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga530ad9fda2ed1c8b70e439ecfe80591f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable a device specific interrupt.  <a href="#ga530ad9fda2ed1c8b70e439ecfe80591f">More...</a><br/></td></tr>
<tr class="separator:ga530ad9fda2ed1c8b70e439ecfe80591f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72f102d31af0ee4aa7a6fb7a180840f3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga72f102d31af0ee4aa7a6fb7a180840f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get a device specific interrupt enable status.  <a href="#ga72f102d31af0ee4aa7a6fb7a180840f3">More...</a><br/></td></tr>
<tr class="separator:ga72f102d31af0ee4aa7a6fb7a180840f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga736ba13a76eb37ef6e2c253be8b0331c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga736ba13a76eb37ef6e2c253be8b0331c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable a device specific interrupt.  <a href="#ga736ba13a76eb37ef6e2c253be8b0331c">More...</a><br/></td></tr>
<tr class="separator:ga736ba13a76eb37ef6e2c253be8b0331c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95a8329a680b051ecf3ee8f516acc662"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga95a8329a680b051ecf3ee8f516acc662"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the pending device specific interrupt.  <a href="#ga95a8329a680b051ecf3ee8f516acc662">More...</a><br/></td></tr>
<tr class="separator:ga95a8329a680b051ecf3ee8f516acc662"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b885147ef9965ecede49614de8df9d2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga3b885147ef9965ecede49614de8df9d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set a device specific interrupt to pending.  <a href="#ga3b885147ef9965ecede49614de8df9d2">More...</a><br/></td></tr>
<tr class="separator:ga3b885147ef9965ecede49614de8df9d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga382ad6bedd6eecfdabd1b94dd128a01a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">NVIC_ClearPendingIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga382ad6bedd6eecfdabd1b94dd128a01a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear a device specific interrupt from pending.  <a href="#ga382ad6bedd6eecfdabd1b94dd128a01a">More...</a><br/></td></tr>
<tr class="separator:ga382ad6bedd6eecfdabd1b94dd128a01a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf4252e600661fd762cfc0d1a9f5b892"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gadf4252e600661fd762cfc0d1a9f5b892"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#gadf4252e600661fd762cfc0d1a9f5b892">More...</a><br/></td></tr>
<tr class="separator:gadf4252e600661fd762cfc0d1a9f5b892"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5bb7f43ad92937c039dee3d36c3c2798"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
<tr class="memdesc:ga5bb7f43ad92937c039dee3d36c3c2798"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the priority for an interrupt.  <a href="#ga5bb7f43ad92937c039dee3d36c3c2798">More...</a><br/></td></tr>
<tr class="separator:ga5bb7f43ad92937c039dee3d36c3c2798"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab18fb9f6c5f4c70fdd73047f0f7c8395"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gab18fb9f6c5f4c70fdd73047f0f7c8395"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the priority of an interrupt.  <a href="#gab18fb9f6c5f4c70fdd73047f0f7c8395">More...</a><br/></td></tr>
<tr class="separator:gab18fb9f6c5f4c70fdd73047f0f7c8395"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0688c59605b119c53c71b2505ab23eb5"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a> (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td></tr>
<tr class="memdesc:ga0688c59605b119c53c71b2505ab23eb5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga0688c59605b119c53c71b2505ab23eb5">More...</a><br/></td></tr>
<tr class="separator:ga0688c59605b119c53c71b2505ab23eb5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3cbca1be7a4726afa9448a9acd89377"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a> (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)</td></tr>
<tr class="memdesc:gad3cbca1be7a4726afa9448a9acd89377"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#gad3cbca1be7a4726afa9448a9acd89377">More...</a><br/></td></tr>
<tr class="separator:gad3cbca1be7a4726afa9448a9acd89377"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaebee9cad6724a5bac1857f0f1fb6d6af"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">NVIC_GetVector</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaebee9cad6724a5bac1857f0f1fb6d6af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Interrupt Vector [not for Cortex-M0, SC000].  <a href="#gaebee9cad6724a5bac1857f0f1fb6d6af">More...</a><br/></td></tr>
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<tr class="memitem:gab43c1c59d5c081f1bc725237f4b1f916"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916">NVIC_SetVector</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t vector)</td></tr>
<tr class="memdesc:gab43c1c59d5c081f1bc725237f4b1f916"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modify Interrupt Vector [not for Cortex-M0, SC000].  <a href="#gab43c1c59d5c081f1bc725237f4b1f916">More...</a><br/></td></tr>
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<tr class="memitem:ga1b47d17e90b6a03e7bd1ec6a0d549b46"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> (void)</td></tr>
<tr class="memdesc:ga1b47d17e90b6a03e7bd1ec6a0d549b46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset the system.  <a href="#ga1b47d17e90b6a03e7bd1ec6a0d549b46">More...</a><br/></td></tr>
<tr class="separator:ga1b47d17e90b6a03e7bd1ec6a0d549b46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62b37611e1ccbac47d747c98ef302746"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746">NVIC_GetTargetState</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga62b37611e1ccbac47d747c98ef302746"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Interrupt Target State.  <a href="#ga62b37611e1ccbac47d747c98ef302746">More...</a><br/></td></tr>
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<tr class="memitem:gaf46218d01a6a3b70666ad0492a7f950a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a">NVIC_SetTargetState</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaf46218d01a6a3b70666ad0492a7f950a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set Interrupt Target State.  <a href="#gaf46218d01a6a3b70666ad0492a7f950a">More...</a><br/></td></tr>
<tr class="separator:gaf46218d01a6a3b70666ad0492a7f950a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44b31316872e91bda1af7e17173de24b"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga44b31316872e91bda1af7e17173de24b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear Interrupt Target State.  <a href="#ga44b31316872e91bda1af7e17173de24b">More...</a><br/></td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Functions to access the Nested Vector Interrupt Controller (NVIC). </p>
<p>This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).</p>
<p>Arm provides a template file <b>startup_<em>device</em></b> for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a <b><em>weak</em></b> function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.</p>
<p>The table below lists the core exception vectors of the various Cortex-M processors.</p>
<table  class="cmtable" summary="Core Exception Name">
<tr>
<th>Exception Vector </th><th>Handler Function </th><th>IRQn<br/>
Value </th><th title="Cortex-M0/M0+
and SC000
      ">Armv6-M </th><th title="Cortex-M3/M4/M7
and SC300
      ">Armv7-M </th><th title="Cortex-M23">Armv8-M<br/>
Baseline </th><th title="Cortex-M33/M35P">Armv8-M<br/>
Mainline </th><th>Armv8.1-M<br/>
Mainline </th><th>Description  </th></tr>
<tr>
<td><b>NonMaskableInt_IRQn</b> </td><td>NMI_Handler </td><td>-14 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Non Maskable Interrupt  </td></tr>
<tr>
<td><b>HardFault_IRQn</b> </td><td>HardFault_Handler </td><td>-13 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Hard Fault Interrupt  </td></tr>
<tr>
<td><b>MemoryManagement_IRQn</b> </td><td>MemManage_Handler </td><td>-12 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Memory Management Interrupt  </td></tr>
<tr>
<td><b>BusFault_IRQn</b> </td><td>BusFault_Handler </td><td>-11 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Bus Fault Interrupt  </td></tr>
<tr>
<td><b>UsageFault_IRQn</b> </td><td>UsageFault_Handler </td><td>-10 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Usage Fault Interrupt  </td></tr>
<tr>
<td><b>SecureFault_IRQn</b> </td><td>SecureFault_Handler </td><td>-9 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Secure Fault Interrupt  </td></tr>
<tr>
<td><b>SVCall_IRQn</b> </td><td>SVC_Handler </td><td>-5 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>SVC Interrupt   </td></tr>
<tr>
<td><b>DebugMonitor_IRQn</b> </td><td>DebugMon_Handler </td><td>-4 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>&#160; </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Debug Monitor Interrupt  </td></tr>
<tr>
<td><b>PendSV_IRQn</b> </td><td>PendSV_Handler </td><td>-2 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>Pend SV Interrupt  </td></tr>
<tr>
<td><b>SysTick_IRQn</b> </td><td>SysTick_Handler </td><td>-1 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td><div class="image">
<img src="check.png"  alt="available"/>
</div>
 </td><td>System Tick Interrupt  </td></tr>
</table>
<h1>Vector Table </h1>
<p>The Vector Table defines the entry addresses of the processor exceptions and the device specific interrupts. It is typically located at the beginning of the program memory, however <a class="el" href="using_VTOR_pg.html">Using Interrupt Vector Remap</a> it can be relocated to RAM. The symbol <b>__Vectors</b> is the address of the vector table in the startup code and the register <b>SCB-&gt;VTOR</b> holds the start address of the vector table.</p>
<p>An Armv8-M implementation with TrustZone provides two vector tables:</p>
<ul>
<li>vector table for Secure handlers</li>
<li>vector table for Non-Secure handlers</li>
</ul>
<p>Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p>
<h2>Processor Exceptions </h2>
<p>At the beginning of the vector table, the initial stack value and the exception vectors of the processor are defined. The vector table below shows the exception vectors of a Armv8-M Mainline processor. Other processor variants may have fewer vectors.</p>
<div class="fragment"><div class="line">__Vectors       DCD     __initial_sp              ; Top of Stack initialization</div>
<div class="line">                DCD     Reset_Handler             ; Reset Handler</div>
<div class="line">                DCD     NMI_Handler               ; NMI Handler</div>
<div class="line">                DCD     HardFault_Handler         ; Hard Fault Handler</div>
<div class="line">                DCD     MemManage_Handler         ; MPU Fault Handler</div>
<div class="line">                DCD     BusFault_Handler          ; Bus Fault Handler</div>
<div class="line">                DCD     UsageFault_Handler        ; Usage Fault Handler</div>
<div class="line">                DCD     SecureFault_Handler       ; Secure Fault Handler</div>
<div class="line">                DCD     0                         ; Reserved</div>
<div class="line">                DCD     0                         ; Reserved</div>
<div class="line">                DCD     0                         ; Reserved</div>
<div class="line">                DCD     SVC_Handler               ; SVC Handler</div>
<div class="line">                DCD     DebugMon_Handler          ; Debug Monitor Handler</div>
<div class="line">                DCD     0                         ; Reserved</div>
<div class="line">                DCD     PendSV_Handler            ; PendSV Handler</div>
<div class="line">                DCD     SysTick_Handler           ; SysTick Handler</div>
</div><!-- fragment --><h2>Device Specific Vectors </h2>
<p>Following the processor exception vectors, the vector table contains also the device specific interrupt vectors.</p>
<div class="fragment"><div class="line">; device specific interrupts</div>
<div class="line">                DCD     WWDG_IRQHandler           ; Window Watchdog</div>
<div class="line">                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect</div>
<div class="line">                DCD     TAMPER_IRQHandler         ; Tamper</div>
</div><!-- fragment --><p>All device specific interrupts should have a default interrupt handler function that can be overwritten in user code. Below is an example for this default handler function.</p>
<div class="fragment"><div class="line">Default_Handler PROC</div>
<div class="line">                EXPORT WWDG_IRQHandler   [WEAK]</div>
<div class="line">                EXPORT PVD_IRQHandler    [WEAK]</div>
<div class="line">                EXPORT TAMPER_IRQHandler [WEAK]</div>
<div class="line">                :</div>
<div class="line">                :</div>
<div class="line">                WWDG_IRQHandler</div>
<div class="line">                PVD_IRQHandler</div>
<div class="line">                TAMPER_IRQHandler</div>
<div class="line">                :</div>
<div class="line">                :</div>
<div class="line">                B .</div>
<div class="line">                ENDP</div>
</div><!-- fragment --><p>The user application may simply define an interrupt handler function by using the handler name as shown below.</p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> WWDG_IRQHandler(<span class="keywordtype">void</span>)</div>
<div class="line">{</div>
<div class="line">  ...</div>
<div class="line">}</div>
</div><!-- fragment --><h1>NVIC Function Usage </h1>
<p>The code below shows the usage of various CMSIS NVIC functions with an LPC1700 device.</p>
<h2>Code Example 1 </h2>
<div class="fragment"><div class="line"><span class="preprocessor">#include &quot;LPC17xx.h&quot;</span></div>
<div class="line"> </div>
<div class="line">uint32_t priorityGroup;                                     <span class="comment">/* Variables to store priority group and priority */</span></div>
<div class="line">uint32_t priority;</div>
<div class="line">uint32_t preemptPriority;</div>
<div class="line">uint32_t subPriority;</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>)  {</div>
<div class="line">  <a class="code" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a>(5);                              <span class="comment">/* Set priority group to 5:</span></div>
<div class="line"><span class="comment">                                                               Bit[7..6] preempt priority Bits, </span></div>
<div class="line"><span class="comment">                                                               Bit[5..3] subpriority Bits </span></div>
<div class="line"><span class="comment">                                                               (valid for five priority bits) */</span></div>
<div class="line">     </div>
<div class="line">  priorityGroup =  <a class="code" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a>();              <span class="comment">/* Get used priority grouping */</span></div>
<div class="line"> </div>
<div class="line">  priority = <a class="code" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a>(priorityGroup, 1, 6);      <span class="comment">/* Encode priority with 6 for subpriority and 1 for preempt priority</span></div>
<div class="line"><span class="comment">                                                               Note: priority depends on the used priority grouping */</span></div>
<div class="line">  <a class="code" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a>(UART0_IRQn, priority);                   <span class="comment">/* Set new priority */</span></div>
<div class="line"> </div>
<div class="line">  priority =  <a class="code" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a>(UART0_IRQn);                 <span class="comment">/* Retrieve priority again */</span>    </div>
<div class="line">  <a class="code" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a>(priority, priorityGroup, &amp;preemptPriority, &amp;subPriority);</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">while</span>(1);</div>
<div class="line">}</div>
</div><!-- fragment --><h2>Code Example 2 </h2>
<div class="fragment"><div class="line"><span class="preprocessor">#include &quot;LPC17xx.h&quot;</span></div>
<div class="line"> </div>
<div class="line">uint32_t active;                                            <span class="comment">/* Variable to store interrupt active state */</span></div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> TIMER0_IRQHandler(<span class="keywordtype">void</span>)  {                             <span class="comment">/* Timer 0 interrupt handler  */</span></div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> (LPC_TIM0-&gt;IR &amp; (1 &lt;&lt; 0))  {                           <span class="comment">/* Check if interrupt for match channel 0 occurred */</span> </div>
<div class="line">    LPC_TIM0-&gt;IR |= (1 &lt;&lt; 0);                               <span class="comment">/* Acknowledge interrupt for match channel 0 occurred */</span></div>
<div class="line">  }</div>
<div class="line">  active = <a class="code" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a>(TIMER0_IRQn);                     <span class="comment">/* Get interrupt active state of timer 0 */</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div>
<div class="line">                                                            <span class="comment">/* Set match channel register MR0 to 1 millisecond */</span></div>
<div class="line">  LPC_TIM0-&gt;MR0 = (((<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000) / 4) - 1);     <span class="comment">/* 1 ms? */</span></div>
<div class="line">   </div>
<div class="line">  LPC_TIM0-&gt;MCR = (3 &lt;&lt; 0);                                 <span class="comment">/* Enable interrupt and reset for match channel MR0 */</span></div>
<div class="line">  <a class="code" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a>(TIMER0_IRQn);                              <span class="comment">/* Enable NVIC interrupt for timer 0 */</span></div>
<div class="line">  LPC_TIM0-&gt;TCR = (1 &lt;&lt; 0);                                 <span class="comment">/* Enable timer 0 */</span></div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">while</span>(1);</div>
<div class="line">}</div>
</div><!-- fragment --><h1>NVIC API Virtualization </h1>
<p>The CMSIS-Core has provisions for overriding NVIC APIs as required for implementing secure systems that control access to peripherals and related interrupts. These overrides allow an operating system to control the access privileges of application code to critical interrupts.</p>
<p>The NVIC function virtualization is enabled with the following #define symbols:</p>
<ul>
<li><a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> enables overriding the CMSIS-Core (Cortex-M) NVIC functions.</li>
<li><a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a> enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions. </li>
</ul>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gadc48b4ed09386aab48fa6b9c96d9034c"></a>
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          <td class="memname">#define CMSIS_NVIC_VIRTUAL</td>
        </tr>
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<p>Virtualization of the NVIC API. </p>
<p>When <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> is defined, the NVIC access functions in the table below must be implemented for virtualizing NVIC access. These functions should be implemented in a separate source module. The original CMSIS-Core __NVIC functions are always available independent of <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a>.</p>
<table class="doxtable">
<tr>
<th>NVIC Access Functions </th><th>CMSIS-Core Functions  </th></tr>
<tr>
<td>NVIC_EnableIRQ </td><td>__NVIC_EnableIRQ </td></tr>
<tr>
<td>NVIC_GetEnableIRQ </td><td>__NVIC_GetEnableIRQ </td></tr>
<tr>
<td>NVIC_DisableIRQ </td><td>__NVIC_DisableIRQ </td></tr>
<tr>
<td>NVIC_GetPendingIRQ </td><td>__NVIC_GetPendingIRQ </td></tr>
<tr>
<td>NVIC_SetPendingIRQ </td><td>__NVIC_SetPendingIRQ </td></tr>
<tr>
<td>NVIC_ClearPendingIRQ </td><td>__NVIC_ClearPendingIRQ </td></tr>
<tr>
<td>NVIC_GetActive </td><td>__NVIC_GetActive </td></tr>
<tr>
<td>NVIC_SetPriority </td><td>__NVIC_SetPriority </td></tr>
<tr>
<td>NVIC_GetPriority </td><td>__NVIC_GetPriority </td></tr>
<tr>
<td>NVIC_SetPriorityGrouping </td><td>__NVIC_SetPriorityGrouping </td></tr>
<tr>
<td>NVIC_GetPriorityGrouping </td><td>__NVIC_GetPriorityGrouping </td></tr>
</table>

</div>
</div>
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          <td class="memname">#define CMSIS_VECTAB_VIRTUAL</td>
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<p>Virtualization of interrupt vector table access functions. </p>
<p>When <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> is defined, the functions in the table below must be replaced to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.</p>
<p>The original CMSIS-Core functions are always available, but prefixed with __NVIC.</p>
<table class="doxtable">
<tr>
<th>Interrupt Vector Table Access </th><th>CMSIS-Core Functions  </th></tr>
<tr>
<td>NVIC_GetVector </td><td>__NVIC_GetVector </td></tr>
<tr>
<td>NVIC_SetVector </td><td>__NVIC_SetVector </td></tr>
</table>

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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></td>
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<p>Definition of IRQn numbers. </p>
<p>The core exception enumeration names for IRQn values are defined in the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a>.</p>
<ul>
<li>Negative IRQn values represent processor core exceptions (internal interrupts).</li>
<li>Positive IRQn values represent device-specific exceptions (external interrupts).</li>
<li>The first device-specific interrupt has the IRQn value 0.</li>
</ul>
<p>The table below describes the core exception names and their availability in various Cortex-M cores. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30"></a>NonMaskableInt_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 2: Non Maskable Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85"></a>HardFault_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 3: Hard Fault Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa"></a>MemoryManagement_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af"></a>BusFault_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf"></a>UsageFault_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da"></a>SecureFault_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 7: Secure Fault Interrupt [only on Armv8-M]. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237"></a>SVCall_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 11: SVC Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c"></a>DebugMonitor_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2"></a>PendSV_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"></a>SysTick_IRQn</em>&#160;</td><td class="fielddoc">
<p>Exception 15: System Tick Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2"></a>WWDG_STM_IRQn</em>&#160;</td><td class="fielddoc">
<p>Device Interrupt 0: Window WatchDog Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86"></a>PVD_STM_IRQn</em>&#160;</td><td class="fielddoc">
<p>Device Interrupt 1: PVD through EXTI Line detection Interrupt. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">void NVIC_ClearPendingIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Clear a device specific interrupt from pending. </p>
<p>This function removes the pending state of the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative number.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>IRQn must not be negative.</li>
<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li>
<li>An interrupt can have the status pending though it is not active.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662" title="Get the pending device specific interrupt. ">NVIC_GetPendingIRQ</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td class="memname">uint32_t NVIC_ClearTargetState </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Clear Interrupt Target State. </p>
<p>Clears the interrupt target field in the non-secure NVIC when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 if interrupt is assigned to Secure</li>
<li>1 if interrupt is assigned to Non Secure </li>
</ul>
</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>Only available for Armv8-M in secure state.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746">NVIC_GetTargetState</a>; <a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a" title="Set Interrupt Target State. ">NVIC_SetTargetState</a>; </li>
</ul>
</dd></dl>

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          <td class="memname">void NVIC_DecodePriority </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>PriorityGroup</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t *&#160;</td>
          <td class="paramname"><em>pPreemptPriority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t *&#160;</td>
          <td class="paramname"><em>pSubPriority</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
<p>This function decodes an interrupt priority value with the priority group <em>PriorityGroup</em> to preemptive priority value <em>pPreemptPriority</em> and subpriority value <em>pSubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">Priority</td><td>Priority </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">*pPreemptPriority</td><td>Preemptive priority value (starting from 0) </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">*pSubPriority</td><td>Subpriority value (starting from 0)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a>; <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt. ">NVIC_GetPriority</a>; <a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. ">NVIC_GetPriorityGrouping</a>;</li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td class="memname">void NVIC_DisableIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Disable a device specific interrupt. </p>
<p>This function disables the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Number of the external interrupt to disable</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>IRQn must not be negative.</li>
<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Enable a device specific interrupt. </p>
<p>This function enables the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>IRQn must not be negative.</li>
<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li>
<li>The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: <br/>
 ICTR[4:0]<ul>
<li>0 - 32 interrupts supported</li>
<li>1 - 64 interrupts supported</li>
<li>...</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a>; <a class="el" href="structSCnSCB__Type.html" title="Structure type to access the System Control and ID Register not in the SCB. ">SCnSCB_Type</a>;</li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>PriorityGroup</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>PreemptPriority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>SubPriority</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
<p>This function encodes the priority for an interrupt with the priority group <em>PriorityGroup</em>, preemptive priority value <em>PreemptPriority</em>, and subpriority value <em>SubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">PreemptPriority</td><td>Preemptive priority value (starting from 0) </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">SubPriority</td><td>Subpriority value (starting from 0)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Encoded priority for the interrupt</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a>; <a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt. ">NVIC_SetPriority</a>;</li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
<p>This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt <em>IRQn</em>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 Interrupt is not active</li>
<li>1 Interrupt is active, or active and pending</li>
</ul>
</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
<li>IRQn must not be negative.</li>
<li>Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.</li>
<li>When an ISR is preempted and the processor executes another interrupt handler, the previous interrupt is still defined as active.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Get a device specific interrupt enable status. </p>
<p>This function returns the interrupt enable status for the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 Interrupt is not enabled</li>
<li>1 Interrupt is enabled</li>
</ul>
</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>IRQn must not be negative.</li>
<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c" title="Disable a device specific interrupt. ">NVIC_DisableIRQ</a>;</li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Get the pending device specific interrupt. </p>
<p>This function returns the pending status of the specified device specific interrupt <em>IRQn</em>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 Interrupt is not pending</li>
<li>1 Interrupt is pending</li>
</ul>
</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>IRQn must not be negative.</li>
<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" title="Clear a device specific interrupt from pending. ">NVIC_ClearPendingIRQ</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
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<p>Get the priority of an interrupt. </p>
<p>This function reads the priority for the specified interrupt <em>IRQn</em>. <em>IRQn</em> can can specify any device specific interrupt, or processor exception.</p>
<p>The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Interrupt priority</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>Each external interrupt has an associated priority-level register.</li>
<li>Unimplemented bits are read as zero.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a>; <a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. ">NVIC_GetPriorityGrouping</a>; <a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_BASEPRI</a>;</li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
</dd></dl>

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          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
<p>This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).</p>
<dl class="section return"><dt>Returns</dt><dd>Priority grouping field</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
<li>By default, priority group setting is zero.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a>; <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt. ">NVIC_GetPriority</a>; <a class="el" href="structSCB__Type.html" title="Structure type to access the System Control Block (SCB). ">SCB_Type</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Get Interrupt Target State. </p>
<p>Reads the interrupt target field from the non-secure NVIC when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 if interrupt is assigned to Secure</li>
<li>1 if interrupt is assigned to Non Secure </li>
</ul>
</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>Only available for Armv8-M in secure state.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a>; <a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a" title="Set Interrupt Target State. ">NVIC_SetTargetState</a>; </li>
</ul>
</dd></dl>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
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<p>Read Interrupt Vector [not for Cortex-M0, SC000]. </p>
<p>This function allows to read the address of an interrupt handler function.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Address of interrupt handler function</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>For using this function with Cortex-M0+ processor based devices, the SBC-&gt;VTOR register must be implemented.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916">NVIC_SetVector</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Set a device specific interrupt to pending. </p>
<p>This function sets the pending bit for the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>IRQn must not be negative.</li>
<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" title="Clear a device specific interrupt from pending. ">NVIC_ClearPendingIRQ</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td class="memname">void NVIC_SetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em>&#160;</td>
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<p>Set the priority for an interrupt. </p>
<p>Sets the priority for the interrupt specified by <em>IRQn</em>.<em>IRQn</em> can can specify any device specific interrupt, or processor exception. The <em>priority</em> specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.</p>
<p>The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt Number </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority to set</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write <em>0xFF</em> to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is <em>0xE0</em>.</li>
<li>Writes to unimplemented bits are ignored.</li>
<li><b>For Cortex-M0</b>:<ul>
<li>Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.</li>
<li>Supports 0 to 192 priority levels.</li>
<li>Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.</li>
</ul>
</li>
<li><b>For Cortex-M3, Cortex-M4, and Cortex-M7</b>:<ul>
<li>Dynamic switching of interrupt priority levels is supported.</li>
<li>Supports 0 to 255 priority levels.</li>
<li>Priority-level registers have a maximum width of 8 bits and a minimum of 3 bits. Each register can be further divided into preempt priority level and subpriority level.</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a>; <a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354" title="Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. ">NVIC_SetPriorityGrouping</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>;</li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td class="memname">void NVIC_SetPriorityGrouping </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>PriorityGroup</em></td><td>)</td>
          <td></td>
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<p>Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
<p>The function sets the priority grouping <em>PriorityGroup</em> using the required unlock sequence. <em>PriorityGroup</em> is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
<li>By default, priority group setting is zero.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a>; <a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt. ">NVIC_SetPriority</a>; <a class="el" href="structSCB__Type.html" title="Structure type to access the System Control Block (SCB). ">SCB_Type</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Set Interrupt Target State. </p>
<p>Sets the interrupt target field in the non-secure NVIC when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 if interrupt is assigned to Secure</li>
<li>1 if interrupt is assigned to Non Secure </li>
</ul>
</dd></dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>Only available for Armv8-M in secure state.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a>; <a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746" title="Get Interrupt Target State. ">NVIC_GetTargetState</a>; </li>
</ul>
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          <td class="memname">void NVIC_SetVector </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>vector</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Modify Interrupt Vector [not for Cortex-M0, SC000]. </p>
<p>This function allows to change the address of an interrupt handler function.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">vector</td><td>Address of new interrupt handler function</td></tr>
  </table>
  </dd>
</dl>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>Usage of this function requires vector relocation to RAM. Refer to <a class="el" href="using_VTOR_pg.html">Using Interrupt Vector Remap</a> for more information.<ul>
<li>For using this function with Cortex-M0+ processor based devices, the SBC-&gt;VTOR register must be implemented.</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">NVIC_GetVector</a></li>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
</ul>
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          <td class="memname">void NVIC_SystemReset </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>Reset the system. </p>
<p>This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.</p>
<dl class="section remark"><dt>Remarks</dt><dd><ul>
<li>In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.</li>
</ul>
</dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> </li>
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